How To Make A Bad Network Analyzer

Introduction

Avast ye lab lubbers and radio farers!

For reasons that will remain disclosed now, I have been getting into designing some measurement instruments. And what better one to talk about than the most coveted item for every radio engineer. The crown jewel, the bank breaker and the deal maker. The network analyzer.

This series will be called “How to design a BAD network analyzer”. This is for several reasons:

  • I would like to understand better thought process of designing such instruments.
  • There are quite a few open-source designs roaming around these days. They vary quite a bit. I don’t want to take any of them for granted.
  • When someone asks me the about the difference between a 50-500$ NA and a 10K$ one, I want to give an educated answer…
  • Learning is evolving. Analog design and board design is definitely outside my usual comfort zone. Every time I step out, something happens. So, let’s see!

The First One (I think)

The first time I was exposed to such a piece of open-source hardware, was about 10 years ago, when this blog post turned up:

https://hforsten.com/cheap-homemade-30-mhz-6-ghz-vector-network-analyzer.html

With painstaking detail and incredible ingenuity, the writer explains how he designs this wonderful piece of equipment. This is just a theory, but not long after I started seeing the first NanoVNA designs. This design suffered from some flaws, naturally, but the thought process described here is as deductive as they come.

Jumping straight to this design, however, may prove tricky to the inadequate board\analog-designer such as myself. So let’s try simplifying this by attempting to design what I assume will be, a very bad network analyzer.

Look Ma, My First Network Analyzer!

Phase measurements are hard. Let’s do something easier. Scalar network analyzers are supposed to be somewhat easier to design. Or I really hope so, at least…

The first building block is, of course, the power detector. Although it should be easy enough to make a power detector “from scratch”, I want something even simpler. A (very) popular choice, readily available at your favorite vendor, is AD8319. So, me being me, let’s to something different. Let’s use the LMH2110. Why? Because it’s a tiny little thing and I like it. Plus, the goal here is to make as many mistakes as possible, and to make a bad network analyzer.

So, since I already have a ready-made design for it from the previous posts, let’s see it:

Schematic for power detector block

Now, connecting two of these, with highly available and useful ADS111x family. Sample time is irrelevant here, only resolution. It’s not the waveform that is sampled, rather the power detector.

For a synthesizer, let’s use (and shame on you if you haven’t guessed this, yet), one of the following:

  • ADF4350\1 – The difference between these two is the lowest obtainable frequency.

Or, his newer counterpart, with the coveted 6 GHz of obtainable frequency

  • MAX2870\1

They have a few discrepancies, but all in all, the surrounding layout is pretty much the same. There are currently some availability issues with the MAX2870 (not that I plan on manufacturing this), so I’ll go with the ADF.

All we need is a couple of directional couplers (or one bi-directional) and voila!

One Port Network Analyzer Block Diagram

One Port Bad, Two Port Good

Well, a one port NA may be very useful as an Antenna analyzer, but not much more. Let’s expand this abomination to a two-port design. For that, we need an RF switch. Two options come to mind:

  • BGSX22G5A10 – This cross switch is one of the coolest devices I came by. Although it’s definitely not a perfect choice, I am tempted to use it because (a) I like it, (b) I want to emphasize the issues of using it.
  • HMC536 – Or something similar, of course. This one, because it works from DC.

Check out the price difference between these two. It may also come into consideration at one point or another. So for argument sake, let’s make a(nother) bad design with the Infineon one, BGSX22G5A10.

2 Port Network Analyzer Block Diagram

The ADS1115 ADC already has 4 inputs, and the power detectors are pretty much dirt cheap, but reducing cost is really the main issue, or just want to conserve space, it is possible to use a 1:4 RF switch to reduce this to a single detector\ADC pair. Why not, this design is bad enough…

Implementing The Blocks

Let’s start from the easiest part. The switch:

Cross switch

Nothing fancy, nothing too tough. Just build and yield. Things start to get funky with the synthesizer.

There is a need, however for a reference signal. If we look at my so-called historic research, you will find that in Henrik’s blog, an Abracon ASTXR-12-19.200MHz was used. It is a temperature compensated crystal oscillator (TCXO). In the NanoVNA 2.x, a programmable quartz oscillator called YSO680PR is used. Seriously, where do they even find these things… A valid alternative from Abracon, for example, will be FC5BS. In the LibreVNA design, another TCXO is used, DSB221SDN 26MHz. However, there it is used as a reference for a different clock generation IC. Why? I don’t know. Why would each component need a different reference signal? We shall find out, later, probably.

Let’s take a moment here to acknowledge the hardship of our brothers and sisters, the hardware engineers. Seriously, how do you begin to cope with this mess? The plethora of different manufacturers\components is astounding. Do you just have favorite vendors and series? Lend your respects, ladies and gentlemen.

So Let’s implement the clock with an Abracon ATX-11-D-26.000MHZ-F10. The ADF\MAX synthesizer can handle a rather wide frequency range, anyway. We have an RF source going on. All that we need now is a D-coupler. These are easy, right? Let’s quickly punch out one using CST:

Coupled Line Directional Coupler
Coupler Performance – S11: Input Return Loss | S21 – Through | S31 – Coupled | S41 – Isolated port (lower is better)

There are a few things to notice. The performance in low frequencies is inadequate, to say the least. The bandwidth is impressive, but if you want something to go up to higher frequencies, a multi-stage design is necessary. These can be rather large, but as long as it delivers good performance, great.

There is more than one solution here, but a very common one is a resistive bridge design. Henrik referenced this article, but this design was actually invented by Joel Dunsmore. He must have been a lot of fun, being probably the smartest person in the building and all…

Dunsmore Coupler

For \mu^{ }‘ and \mu^{''} I used figures found in an article characterizing MnZn ferrites.

MnZn Ferrite Parameters

There are no free meals. Where this design “enjoys” an impressive bandwidth, it suffers with insertion loss. However, take a look at the flatness of the response, especially in the low frequencies. It is also much more directive (in this case, the difference between S_{32} and S_{31}), but I’m guessing I can optimize both couplers a bit more.

Dunsmore Coupler Performance

In logarithmic scale it’s even more impressive

Comparison Between the Two Couplers

Just for fairness sake, what did the other open-source designs do? In the NanoVNA they used a couple of SMD transformers. It is unclear if it was the TOKO 617DB-1023 or the YAGEO CX2156NL. I’m guessing the latter. Both aren’t even rated anywhere near 4.4 GHz, but who cares.

For the LibreVNA… You got to hand it to the guy, I have no idea where he sources these. He used a very nifty transformer called B012-617DB-2-43-B331. It is rated up to 4 GHz, and can probably go up even higher.

I’m going to go with the resistive bridge design, for two reasons:

One more block to go: The ADC. Here I (re-)used the ADS1115, by TI

ADS 1115 – ADC for power detector sampling

Gotta love these drag-and-drop items…

Network Analyzer Block Diagram

A Short Shortlist of Everything Wrong

All you critical readers, prepare your keyboards. Put some moisturizer on these hands and let it roll out. There are hardly any points light in this design. Practically everything is wrong. Let’s focus on a couple:

At best, it is possible to obtain about 20dB. There is no output power leveling anywhere, which is critical for a design like this. For example, say the synthesizer outputs -10dBm, we have lost 10 decibels immediately off the  range obtainable with the LMH2110. Now insert a  directional coupler into the equation, with  insertion loss, this puts it in a very bad place.

Also, a short inspection of these devices will show that their matching degrades over frequency. This can also affect the dynamic range for some extent.

The isolation, is, of course, the result of the weakest chain in the link. Here, this is due to one design choice – The switch. The characteristic isolation between ports of the switch can range between 60dB to 29dB. Although 60dB is Ok-ish, 29dB is unacceptable. Commercial VNAs can go below a dynamic range of -90dB. If we want to get close to that, every design choice has to account for that.

This design doesn’t detect phase. I know, I’m being captain obvious here, but as I’ll review in the next series of posts, the techniques employed to allow phase measurement are actually better for amplitude measurement, as well.

Conclusion

All this goes to saying. Everything isn’t terrible here. For learning the basic principles of a network analyzer, this is a pretty good kickoff. It gives some sort of idea about the timeframes it takes to design the various blocks. Most of them are pretty simple, but some of the supposedly simple ones, e.g. the coupler, took alot longer than expected. I haven’t even gotten to integrating an MCU yet.

Also, I wanted to try out the Dunsmore coupler for quite a while now. I found about the more modern JESD204 protocol, which is really interesting, as well as a myriad of alternative components for everything.

This was it for the series of making a bad VNA. The next series of posts on this subject will be how to make a mediocre VNA. If you want a good one, you’ll have to put up the respective amount. Now you have a slightly better idea regarding why they cost so much…

Hope you enjoyed!

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