In the last few months, I had the chance to help with de-embedding problems in Chip measurements. Although the physical models that these methods make use of are slightly different, there is one sin that is consistent across all of them.
Usually a de-embedding method applies a physical model that best depicts the adapter to the Device Under Test (DUT)
followed by a feeble attempt to extract said physical model. One very common model is a 2nd order, such as:
This model depicts best a shunt capacitance to the ground, followed by a short wire\trace simulating a short length of trace. One common de-embedding technique is to manufacture an open and short structure,
and perform an analytical calculation to extract the shunt\series loads, for example:
Did you notice the sin? Did you????
We referred to the load as a true-open load. This works well only in very specific cases, when the capacitance is very low, or at least the shunt impedance is very high. For example, very low frequencies, where the system is already considered lumped. Well that’s not impressive, isn’t it… It means we are probably doing only mildly better then assuming the system is already lumped.
Naturally, the same can be said regarding the short reference load. Two factors come into play here. One is that the short is never ideal. There is always a short distance connecting between the adapter and the ground. The second is that the shorting out is no-ideal, as well.
I’m exaggerating, of course. These techniques work well so far and are vastly used around the industry. Also, they perform with various levels of credibility with respect to different stackups (layer structures).
There is no epic conclusion here, but one must be aware of the limitations when using such techniques. Utilizing simulated tools to better predict the actual open\load impedance is sometimes a good choice, as well as implementing different de-embedding techniques, e.g. multi-line.
Although this is far from a profound explanation, it is an important point to emphasize.
Enjoy!